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oki semiconducto r fedd56v16160j-07 issue date: oct. 26, 2005 msm56v16160j 2-bank 524,288-word 16-bit synchronous dynamic ram 1/34 description the msm56v16160j is a 2-bank 524,288-word 16-bit synchronous dynamic ram. the device operates at 3.3v. the inputs and outputs are lvttl compatible. features ? silicon gate, quadruple polysilicon cmos, 1-transistor memory cell ? 2-bank 524,288-word 16-bit configuration ? single 3.3 v power supply, 0.3 v tolerance ? input : lvttl compatible ? output : lvttl compatible ? refresh : 4096 cycles/64 ms ? programmable data transfer mode - cas latency (2, 3) - burst length (1, 2, 4, 8, full page) - data scramble (sequential, interleave) ? auto-refresh, self-refresh capability ? packages: 50-pin 400mil plastic tsop(typeii) (tsopii50-p-400-0.80-k) (product:msm56v16160j-xxts-k) (product:msm56v16160j-xxt3-k) xx indicates speed rank. product family access time (max.) family max. frequency t ac2 t ac3 msm56v16160j-75 133mhz 5.4ns 5.4ns msm56v16160j-8 125mhz 6ns 6ns msm56v16160j-10 100mhz 6ns 6ns
fedd56v16160j-07 oki semiconductor msm56v16160j 2/34 pin configuration (top view) pin name function pin name function clk system clock udqm, ldqm data input / output mask cs chip select dqi data input / output cke clock enable v cc power supply (3.3v) a0?a10 address v ss ground (0v) a11 bank select address v cc q data output power supply (3.3v) ras row address strobe v ss q data output ground (0v) cas column address strobe nc no connection we write enable note : the same power supply voltage must be provided to every v cc pin . the same power supply voltage must be provided to every v cc q pin. the same gnd voltage level must be provided to every v ss pin and v ss q pin. 24 19 20 21 22 23 14 15 16 17 18 7 44 37 36 35 34 33 32 31 30 29 28 27 a11 a10 v ss q v cc qv cc q v ss nc udqm nc a 8 a 7 a 6 we cas ras cs a0 a1 a2 ldqm a 5 a 4 clk cke 1 2 3 4 5 6 8 9 10 11 12 13 50 49 48 47 46 45 43 42 41 40 39 38 dq1 dq2 v cc v cc q v ss v cc q dq13 dq12 dq11 v ss q dq6 v ss q dq7 dq8 dq3 dq4 dq5 dq10 dq9 dq14 dq16 dq15 v ss q a3 a 9 26 25 v cc 50-pin plastic tsop ( ii ) (k type)
fedd56v16160j-07 oki semiconductor msm56v16160j 3/34 pin description clk fetches all inputs at the ?h? edge. cs disables or enables device operation by asserti ng or deactivating all inputs except clk, cke, udqm and ldqm. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, system clock will be ma sked so that the subsequent clk operation is deactivated. cke should be asserted at least one cycle prior to a new command. address row & column multiplexed. row address : ra0 ? ra10 column address : ca0 ? ca7 a11 slects bank to be activated during row addre ss latch time and selects bank for precharge and read/write during column address latch time . a11=?l? : bank a, a11=?h? : bank b ras cas we functionality depends on the combination. for details, see the function truth table. udqm, ldqm masks the read data of two clocks later when udqm and ldqm are set ?h? at the ?h? edge of the clock signal. masks the write data of the same clock when udqm and ldqm are set ?h? at the ?h? edge of the clock signal. udqm controls upper byte and ldqm controls lower byte. dqi data inputs/outputs are multiplexed on the same pin.
fedd56v16160j-07 oki semiconductor msm56v16160j 4/34 electrical characteristics absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in , v out ?0.5 to v cc + 0.5 v v cc supply voltage v cc , v cc q ?0.5 to 4.6 v storage temperature t stg ?55 to 150 c power dissipation p d* 1000 mw short circuit output current i os 50 ma operating temperature t opr 0 to 70 c *: ta = 25 c recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min. typ. max. unit power supply voltage v cc , v cc q 3.0 3.3 3.6 v input high voltage v ih 2.0 ? v cc + 0.3 v input low voltage v il ? 0.3 ? 0.8 v pin capacitance (v bias = 1.4 v, ta = 25c, f = 1 mhz) parameter symbol min. max. unit input capacitance (clk) c clk ? 4 pf input capacitance (cke, a0 ? a11, cs , ras , cas , we , udqm, ldqm ) c in ? 5 pf input/output capacitance (dq1 ? dq16) c out ? 6.5 pf
fedd56v16160j-07 oki semiconductor msm56v16160j 5/34 dc characteristics (1/2) msm56v16160j condition -75 -8 parameter symbol bank cke others min. max. min. max. unit note output high voltage v oh ? ? i oh = ? 2.0ma 2.4 ? 2.4 ? v output low voltage v ol ? ? i ol =2.0ma ? 0.4 ? 0.4 v input leakage current i li ? ? ? ? 10 10 ? 10 10 a output leakage current i lo ? ? ? ? 10 10 ? 10 10 a average power supply current (operating) i cc1 one bank active cke v ih t cc = min. t rc = min. no burst ? 90 ? 80 ma 1,2 power supply current (standby) i cc2 both banks precharge cke v ih t cc = min. ? 35 ? 35 ma 3 average power supply current (clock suspension) i cc3s both banks active cke v il t cc = min. ? 3 ? 3 ma 2 average power supply current (active standby) i cc3 one bank active cke v ih t cc = min. ? 40 ? 40 ma 3 power supply current (burst) i cc4 both banks active cke v ih t cc = min. ? 130 ? 120 ma 1,2 power supply current (auto-refresh) i cc5 one bank active cke v ih t cc = min. t rc = min. ? 130 ? 120 ma 2 average power supply current (self-refresh) i cc6 both banks precharge cke v il t cc = min. ? 2 ? 2 ma average power supply current (power down) i cc7 both banks precharge cke v il t cc = min. ? 2 ? 2 ma
fedd56v16160j-07 oki semiconductor msm56v16160j 6/34 dc characteristics (2/2) msm56v16160j condition -10 parameter symbol bank cke others min. max. uni t note output high voltage v oh ? ? i oh = ? 2.0ma 2.4 ? v output low voltage v ol ? ? i ol =2.0ma ? 0.4 v input leakage current i li ? ? ? ? 10 10 a output leakage current i lo ? ? ? ? 10 10 a average power supply current (operating) i cc1 one bank active cke v ih t cc = min. t rc = min. no burst ? 70 ma 1,2 power supply current (standby) i cc2 both banks precharge cke v ih t cc = min. ? 30 ma 3 average power supply current (clock suspension) i cc3s both banks active cke v il t cc = min. ? 3 ma 2 average power supply current (active standby) i cc3 one bank active cke v ih t cc = min. ? 35 ma 3 power supply current (burst) i cc4 both banks active cke v ih t cc = min. ? 100 ma 1,2 power supply current (auto-refresh) i cc5 one bank active cke v ih t cc = min. t rc = min. ? 100 ma 2 average power supply current (self-refresh) i cc6 both banks precharge cke v il t cc = min. ? 2 ma average power supply current (power down) i cc7 both banks precharge cke v il t cc = min. ? 2 ma notes: 1. measured with outputs open. 2. the address and data can be changed once or left unchanged during one cycle. 3. the address and data can be changed once or left unchanged during two cycles.
fedd56v16160j-07 oki semiconductor msm56v16160j 7/34 mode set address keys write mode cas latency burst type burst length a9 wm a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 0 burst 0 0 0 reserved 0 sequential 0 0 0 1 1 1 single 0 0 1 1 * 1 interleave 0 0 1 2 2 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 reserved 1 0 0 reserved reserved 1 0 1 reserved 1 0 1 reserved reserved 1 1 0 reserved 1 1 0 reserved reserved 1 1 1 reserved 1 1 1 full page *2 reserved *: cl=1 mode operation is not guaranteed notes: 1.a7, a8, a10 and a11 should stay ?l? during mode set cycle. 2.column address is repeated until terminated. msm56v16160j support two methods of power on sequence. power on sequence 1 1. with inputs in nop state and cke=high, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply a auto-refresh eight or more times. 5. enter the mode register setting command. power on sequence 2 1. with inputs in nop state and cke=high, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. enter the mode register setting command. 5. apply a auto-refresh eight or more times.
fedd56v16160j-07 oki semiconductor msm56v16160j 8/34 ac characteristics (1/4) note1, 2 msm56v16160j -75 -8 parameter symbol min. max. min. max. unit note cl = 3 t cc3 7.5 ? 8 ? ns clock cycle time cl = 2 t cc2 10 ? 10 ? ns cl = 3 t ac3 ? 5.4 ? 6 ns 3,4 access time from clock cl = 2 t ac2 ? 5.4 ? 6 ns 3,4 clock high pulse time t ch 2.5 ? 3 ? ns 4 clock low pulse time t cl 2.5 ? 3 ? ns 4 input setup time t si 1.5 ? 2 ? ns input hold time t hi 0.8 ? 1 ? ns output low impedance time from clock t olz 3 ? 3 ? ns output high impedance time from clock t ohz ? 5.4 ? 6 ns output hold from clock t oh 3 ? 3 ? ns 3 random read or write cycle time t rc 65 ? 70 ? ns ras precharge time t rp 20 ? 20 ? ns ras pulse width t ras 45 100,000 50 100,000 ns ras to cas delay time t rcd 20 ? 20 ? ns write recovery time t wr 10 ? 10 ? ns ras to ras bank active delay time t rrd 10 ? 10 ? ns refresh time t ref ? 64 ? 64 ms 6 power-down exit setup time t pde t si +1clk ? t si +1clk ? ns input level transition time t t ? 3 ? 3 ns cas to cas delay time (min.) l ccd 1 1 cycle clock disable time from cke l cke 1 1 cycle data output high impedance time from udqm, ldqm l doz 2 2 cycle dada input mask time from udqm, ldqm l dod 0 0 cycle
fedd56v16160j-07 oki semiconductor msm56v16160j 9/34 ac characteristics (2/4) note1, 2 msm56v16160j -75 -8 parameter symbol min. max. min. max. unit note data input mask time from write command l dwd 0 0 cycle data output high impedance time from precharge command l roh cl cl cycle active command input time from mode register set command input (min.) l mrd 2 2 cycle write command input time from output l owd 2 2 cycle
fedd56v16160j-07 oki semiconductor msm56v16160j 10/34 ac characteristics (3/4) note1, 2 msm56v16160j -10t s-k parameter symbol min. max. unit note cl = 3 t cc3 10 ? ns clock cycle time cl = 2 t cc2 10 ? ns cl = 3 t ac3 ? 6 ns 3,4 access time from clock cl = 2 t ac2 ? 6 ns 3,4 clock high pulse time t ch 3 ? ns 4 clock low pulse time t cl 3 ? ns 4 input setup time t si 2 ? ns input hold time t hi 1 ? ns output low impedance time from clock t olz 3 ? ns output high impedance time from clock t ohz ? 6 ns output hold from clock t oh 3 ? ns 3 random read or write cycle time t rc 70 ? ns ras precharge time t rp 20 ? ns ras pulse width t ras 50 100,000 ns ras to cas delay time t rcd 20 ? ns write recovery time t wr 10 ? ns ras to ras bank active delay time t rrd 20 ? ns refresh time t ref ? 64 ms 6 power-down exit setup time t rde t si +1clk ? ns input level transition time t t ? 3 ns cas to cas delay time (min.) l ccd 1 cycle clock disable time from cke l cke 1 cycle data output high impedance time from udqm, ldqm l doz 2 cycle dada input mask time from udqm, ldqm l dod 0 cycle
fedd56v16160j-07 oki semiconductor msm56v16160j 11/34 ac characteristics (4/4) note 1,2 msm56v16160j -10t s-k parameter symbol min. max. unit note data input mask time from write command l dwd 0 cycle data output high impedance time from precharge command l roh cl cycle active command input time from mode register set command input (min.) l mrd 2 cycle write command input time from output l owd 2 cycle notes: 1. ac measurements assume that v ih = 2.4v, v il = 0.4v and t t = 1ns,. 2. the reference level for timing of input signals is 1.4v. 3. output load. 4. the access time is defined at 1.4v. 5. if t t is longer than 1ns, then the reference level for timing of input signals is v ih and v il . 6. it is necessary to operate auto-refresh 4096 cycles within tref. output z=50 ? 50pf (external load) 1.4v 50 ?
fedd56v16160j-07 oki semiconductor msm56v16160j 12/34 timing chart read & write cycle (same bank) @ cas latency = 2, burst length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm t oh ra ca0 t rp t rc qa1 cb0 rb rb ra qa0 qa2 qa3 db0 db1 db2 db3 t ac t ohz row active read command prechar g e command row active write command prechar g e command t rcd
fedd56v16160j-07 oki semiconductor msm56v16160j 13/34 single bit read-write-rea d cycle (same page) @ cas latency = 2, burst length = 4 clk cke c s r as c as addr a11 a10 dq w e udqm, ld q m row active 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t olz db t si qc t hi qa t oh ra l owd bs bs bs bs bs ra cc cb ca t ohz t ac t hi t si t si t hi t hi t si t si t hi t hi t si i ccd t si t cl t cc t ch read command write command read command prechar g e command
fedd56v16160j-07 oki semiconductor msm56v16160j 14/34 *notes: 1. when cs is set ?high? at a clock transition from ?low? to ?high?, all inputs except cke, udqm and ldqm are invalid. 2. when issuing an active, read or write command, the bank is selected by a11. a11 active, read or write 0 bank a 1 bank b 3. the auto precharge function is enabled or disabled by the a10 input when the read or write command is issued. a10 a11 operation 0 0 after the end of burst, bank a holds the row-active status. 1 0 after the end of burst, bank a is precharged automatically. 0 1 after the end of burst, bank b holds the row-active status. 1 1 after the end of burst, bank b is precharged automatically. 4. when issuing a precharge command, the bank to be precharged is selected by the a10 and a11 inputs. a10 a11 operation 0 0 bank a is precharged. 0 1 bank b is precharged. 1 x both banks a and b are precharged. 5. the input data and the write command are latched by the same clock (write latency = 0). 6. the output is forced to high impedance by (1clk+ t ohz ) after udqm, ldqm entry.
fedd56v16160j-07 oki semiconductor msm56v16160j 15/34 page read & write cycle (same bank) @ cas latency = 2, burst length = 4 *notes: 1. to write data before a burst read ends, udqm and ldqm should be asserted three cycles prior to the write command to avoid bus contention. 2. to assert row precharge before a burst write ends, wait t wr after the last write data input. input data during the precharge input cycle will be masked internally. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm read command read command write command write command prechar g e command qa0 qa1 qb0 qb1 dc0 dc1 dd0 cc0 cd0 ca0 cb0 t wr i ccd ? note 2 ? note 1 bank a active l owd high
fedd56v16160j-07 oki semiconductor msm56v16160j 16/34 read & write cycle with auto precharge @ burst length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as addr a11 a10 w e a -bank prechar g e start row active (b-bank) a bank read with auto precharge b bank write with auto precharge b bank precharge start point a -bank prechar g e start high ra t rrd t wr rb ra rb ca cb db0 db1 db2 db3 qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 c as latenc y =2 c as latenc y =3 row active (a-bank) dq dq udqm, ldqm udqm, ldqm
fedd56v16160j-07 oki semiconductor msm56v16160j 17/34 bank interleave random row read cycle @ cas latency = 2, burst length = 4 clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa caa rbb cbb rac cac raa rbb rac qaa0 qaa1 qaa2 qaa3 qbb1 qbb2 qbb3 qbb4 qac0 qac1 qac2 qac3 row active (a-bank) read command (a-bank) precharge command (a-bank) row active (b-bank) read command (b-bank) precharge command (b-bank) row active (a-bank) read command (a-bank) t rrd t rc high
fedd56v16160j-07 oki semiconductor msm56v16160j 18/34 bank interleave rando m row write cycle @ cas latency = 2, burst length = 4 clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa caa rbb cbb rac cac raa rbb rac daa0 daa1 daa2 daa3 row active (a-bank) write command (a-bank) precharge command (a-bank) row active (b-bank) write command (b-bank) precharge command (b-bank) row active (a-bank) write command (a-bank) dbb0 dbb1 dbb2 dbb3 dac0 dac1 high precharge command (a-bank)
fedd56v16160j-07 oki semiconductor msm56v16160j 19/34 bank interleave page read cycle @ cas latency = 2, burst length = 4 *note: 1. cs is ignored when ras , cas and we are high at the same cycle. clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa caa rbb cbb cac cbd cae raa rbb qaa0 qaa1 qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1 ? note 1 row active (a-bank) read command (a-bank) row active (b-bank) read command (b-bank) precharge command (a-bank) read command (a-bank) read command (a-bank) read command (b-bank) i roh high
fedd56v16160j-07 oki semiconductor msm56v16160j 20/34 bank interleave page write cycle @ cas latency = 2, burst length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm row active (a-bank) row active (b-bank) write command (a-bank) precharge command (both bank) high raa caa raa rbb rbb cbd daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 dbd0 write command (b-bank) write command (a-bank) write command (b-bank) daa2 daa1 daa0 cac cbb
fedd56v16160j-07 oki semiconductor msm56v16160j 21/34 bank interleave random row read/write cycle @ cas latency = 2, burst length = 4 clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa caa rbb cbb rac cac raa rbb rac qaa0 qaa1 qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qac2 qac3 row active (a-bank) read command (a-bank) precharge command (a-bank) row active (b-bank) write command (b-bank) row active (a-bank) read command (a-bank) high
fedd56v16160j-07 oki semiconductor msm56v16160j 22/34 bank interleave page read/write cycle @ cas latency = 2, burst length = 4 clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 caa0 cbb0 cac 0 qaa0 qaa1 qaa2 qaa3 read command (a-bank) write command (b-bank) read command (a-bank) dbb0 dbb1 dbb2 dbb3 qac0 qac1 high qac2 qac3
fedd56v16160j-07 oki semiconductor msm56v16160j 23/34 clock suspension & dqm operation cycle @ cas latency = 2, burst length = 4 *note: 1. when clock suspension is asserted, the next clock cycle is ignored. 2. when udqm and ldqm are asserted, the read data after two clock cycles is masked. 3. when udqm and ldqm are asserted, the write data in the same clock cycle is masked. 4. when ldqm is set high, the input/output data of dq1 ? dq8 is masked. 5. when udqm is set high, the input/output data of dq9 ? dq16 is masked. clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ra ca cb cc ra qa0 qa1 qa2 qb0 qb1 dc0 ? note 1 row active read command clock suspension read dqm clock suspension read command write command read dqm ? note 1 ? note 2 ?
fedd56v16160j-07 oki semiconductor msm56v16160j 24/34 read to write cycle (same bank) @ cas latency = 2, burst length = 4 *note: 1. in case cas latency is 3, read can be interrupted by write. the minimum command interval is [burst length + 1] cycles. udqm, ldqm must be high at least 3 clocks prior to the write command. clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ra ca0 cb0 ra db0 db1 ? note 1 row active read command write command precharge command t wr t rcd db2 db3 da0
fedd56v16160j-07 oki semiconductor msm56v16160j 25/34 read interruption by prechar ge command @burst length = 8 *note: 1. if row precharge is asserted before a burst read ends, then the read data will not output after l roh equals cas latency. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as addr a11 a10 w e c as latenc y =2 c as latenc y =3 ra ca ra ? note 1 qa0 qa1 qa2 qa3 qa4 qa5 ? note 1 qa0 qa1 qa2 qa3 qa4 row active read command precharge command l roh qa5 l roh high dq dq udqm, ldqm udqm, ldqm
fedd56v16160j-07 oki semiconductor msm56v16160j 26/34 burst stop command @burst length = 8 clk cke c s r as c as addr a11 a10 w e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 c as latenc y = 2 c as latenc y = 3 qa0 qa1 qa2 qa3 qa4 qa0 qa1 qa2 qa3 qa4 read command cb qb0 qb1 qb2 qb3 qb4 qb0 qb1 qb2 qb3 qb4 burst sto p command write command burst stop command high ca dq dq udqm, ldqm udqm, ldqm
fedd56v16160j-07 oki semiconductor msm56v16160j 27/34 power down mode @cas latency = 2, burst length = 4 *note: 1. when both banks are in precharge state, and if cke is set low, then the msm56v16160j enters power-down mode and maintains the mode while cke is low. 2. to release the circuit from power-down mode, cke has to be set high for longer than t pde (t si + 1clk). clk cke c s r as c as addr a11 a10 dq w e udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ra ca ra qa0 qa1 qa2 ? note 2 power-down entry row active power-down exit precharge command read command clock suspension exit t si ? note 1 clock suspension entry t pde t si t si t ref (min.)
fedd56v16160j-07 oki semiconductor msm56v16160j 28/34 self refresh cycle 0 1 2 clk cke c s r as c as addr a11 a10 dq w e udqm, ld q m ra bs ra self refresh entry self refresh exit row active t si t rc hi-z
fedd56v16160j-07 oki semiconductor msm56v16160j 29/34 mode register set cycle auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 clk cke c s r as c as addr dq w e udqm, ldqm new command l mrd auto refresh t rc mrs auto refresh key ra hi - z hi - z high high 0 1 2 3 4 5 6
fedd56v16160j-07 oki semiconductor msm56v16160j 30/34 function truth table (table 1) (1/2) current state 1 cs ras cas we ba addr action h x x x x x nop l h h h x x nop l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra row active l l h l ba a10 nop 4 l l l h x x auto-refresh or self-refresh 5 idle l l l l l op code mode register write h x x x x x nop l h h x x x nop l h l h ba ca, a10 read l h l l ba ca, a10 write l l h h ba ra illegal 2 l l h l ba a10 precharge row active l l l x x x illegal h x x x x x nop (continue row active after burst ends) l h h h x x nop (continue row active after burst ends) l h h l x x term burst --> row active l h l h ba ca, a10 term burst, start new burst read 3 l h l l ba ca, a10 term burst, start new burst write 3 l l h h ba ra illegal 2 l l h l ba a10 term burst, execute row precharge read l l l x x x illegal h x x x x x nop (continue row active after burst ends) l h h h x x nop (continue row active after burst ends) l h h l x x term burst --> row active l h l h ba ca, a10 term burst, start new burst read 3 l h l l ba ca, a10 term burst, start new burst write 3 l l h h ba ra illegal 2 l l h l ba a10 term burst, execute row precharge 3 write l l l x x x illegal h x x x x x nop (continue burst to end and enter row precharge) l h h h x x nop (continue burst to end and enter row precharge) l h h l ba x illegal 2 l h l h ba ca, a10 illegal 2 l h l l x x illegal l l h x ba ra, a10 illegal 2 read with auto precharge l l l x x x illegal h x x x x x nop (continue burst to end and enter row precharge) l h h h x x nop (continue burst to end and enter row precharge) l h h l ba x illegal 2 write with auto precharge l h l h ba ca, a10 illegal 2
fedd56v16160j-07 oki semiconductor msm56v16160j 31/34 function truth table (table 1) (2/2) current state 1 cs ras cas we ba addr action l h l l x x illegal l l h x ba ra, a10 illegal 2 write with auto precharge l l l x x x illegal h x x x x x nop --> idle after t rp l h h h x x nop --> idle after t rp l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 nop 4 precharge l l l x x x illegal h x x x x x nop l h h h x x nop l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 illegal 2 write recovery l l l x x x illegal h x x x x x nop --> row active after t rcd l h h h x x nop --> row active after t rcd l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 illegal 2 row active l l l x x x illegal h x x x x x nop --> idle after t rc l h h x x x nop --> idle after t rc l h l x x x illegal l l h x x x illegal refresh l l l x x x illegal h x x x x x nop l h h h x x nop l h h l x x illegal l h l x x x illegal mode register access l l x x x x illegal abbreviations ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge ? notes : 1. all inputs are enabled when cke is se t high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. satisfy the timing of l ccd and t wr to prevent bus contention. 4. nop to bank precharging or in idle state. precharges activated bank by ba or a10. 5. illegal if any bank is not idle.
fedd56v16160j-07 oki semiconductor msm56v16160j 32/34 function truth table for cke (table 2) current state (n) cken-1 cken cs ras cas we add r action h x x x x x x invalid l h h x x x x exit self refresh --> abi 6,8 l h l h h h x exit self refresh --> abi 6,8 l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x nop (maintain self refresh) h x x x x x x invalid l h h x x x x exit power down --> abi l h l h h h x exit power down --> abi l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal 7 power down l l x x x x x nop (continue power down mode) h h x x x x x refer to table 1 h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l h l x illegal h l l l l h x enter self refresh h l l l l l x illegal all banks idle (abi) l l x x x x x nop h h x x x x x refer to operations in table 1 h l x x x x x begin clock suspend next cycle l h x x x x x enable clock of next cycle any state other than listed above l l x x x x x continue clock suspension *notes : 6. if the minimum cycle time t rc is satisfied after issuing self-refresh-exit , all banks will be in idle state. 7. if the minimum set-up time t pde is satisfied when cke transition from ?l? to ?h?, cke operates asynchronously so that a command can be input in the same internal clock cycle. 8. if the system uses burst auto refresh during normal operation, it is recommended to use burst 4096 auto refresh cycles immediately after exiting in self refresh mode.
fedd56v16160j-07 oki semiconductor msm56v16160j 33/34 revision history page document no. date previous edition current edition description fedd56v16160j-01 oct. 6, 2004 ? ? first edition fedd56v16160j-02 oct. 14, 2004 ? ? from fedd56v16160jfg-02 fedd56v16160j-03 oct. 19, 2004 ? ? xxtk-fg ->> xxts-k fedd56v16160j-04 mar. 22, 2005 ? 1, 10, 11 added 6 rank (166mhz) fedd56v16160j-05 jun. 9 2005 4 block diagram deleted fedd56v16160j-06 jul. 20 2005 1 1 title erratum revised fedd56v16160j-07 oct. 26 2005 1, 5, 9, 10 1 6 rank and 7 rank deleted
fedd56v62160e-01 oki semiconductor md56v62160e 34/34 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended fo r use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for us e in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, tr affic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2005 oki electric industry co., ltd.

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